An easier start for UVM, take two

By Chris Edwards |  No Comments  |  Posted: November 19, 2013
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users. The upcoming release will include a code generator alongside an updated set of guidelines.

John Aynsley, cofounder and CTO of Doulos, said at the Verification Futures conference organised by Test and Verification Solutions this week (19 November): “It would be good to establish a methodology on top of UVM. This is one step in that direction.”

Aynsley said that, although the growth in the adoption of SystemVerilog and UVM has been strong, UVM suffers from being too complicated to put into action quickly. “When you have learned everything in UVM you need to know to get started, you are still not ready to use it in anger,” he said, noting that the richness of features in UVM proves a drawback for organizations beginning the move, who are likely to be smaller operations than the early adopters.

“UVM is being pushed out to a wider and wider range of designers. For the biggest guys it’s all easy. The biggest players tend to be very active on the committees. The result is that some of the things that go into UVM become part of an early adopter’s sandpit and which solve specific problems of those early adopters,” Aynsley argued, adding that Easier UVM is a reaction to this trend, putting emphasis on features in the standard that apply to a wide range of verification users.

After the first iteration

Doulos introduced the Easier UVM template at DVCon in 2011. “It was mainly aimed at mainstream Verilog and VHDL users, reducing UVM to a clean set of concepts. We start with a subset of classes. It’s still UVM but makes it a little more approachable for the wider pool of UVM adopters who are not necessarily verification experts,” Aynsley explained. “Now we are moving onto the second version of Easier UVM. It goes further by adding a set of specific coding guidelines and an automated code generator.

“Many people have their own Perl scripts or code generators to get things going. We’ve just come up with one to get new users started. It also helps with productivity. Our initial measurement is that it can cut six man weeks off the beginning of the schedule as you create the UVM code base. It also helps you use UVM consistently across the organization.”

“The coding guidelines are mainly common sense. We’ve had a lot of experience in seeing how people use UVM. And we have come up with something more prescriptive than the official [UVM] user guide or the class reference,” Aynsley said. The guidelines cover aspects such as naming conventions and “which macros to use and which not to use, as well as coding patterns to use in specific, common situations. There are also guidelines on how to structure a verification environment”.

Template code generation

“With the code generator, you feed it a set of text files that pin down the specifics of your design, such as interface names and so on. It spits out a directory structure and example code that is populated with placeholders that you will want to replace with your own code but will at least get you started.

“It’s still only 10 to 20 per cent of your total work because a lot will be project specific but this will get you started,” Aynsley claimed.

Aynsley said the code generator will be released under an open-source licence and that the guidelines will be published online. The release date is uncertain but is likely to be within the next two or three months.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors