The latest release of the Riviera-Pro verification tool from Aldec sees the company extend its support for VHDL, which remains a popular choice among programmable-logic users even if support from the device makers themselves has shifted away from the language in recent years.
In January, the company joined with Synthworks to launch a verification methodology for VHDL that mirrors the Universal Verification Methodology (UVM) that was built around SystemVerilog. With the 2012.02 release, Aldec has added some IEEE 1076-2008 language features that improve its handling of testbenches designed to use the Open Source VHDL Verification Methodology (OS-VVM).
OS-VVM brings a number of features from the UVM world – primarily the use of constrained random verification – into that of VHDL with an extra wrinkle of its own: the ability to use functional coverage results to tweak the way random stimuli are created and so, if set up correctly, focus simulation cycles on parts of the design that have not been covered so well.
The latest release of Riviera Pro adds features for SystemVerilog and UVM, given the support in the ASIC industry for SystemVerilog, but with a large body of FPGA users wanting to stick with VHDL, Aldec vice president Dave Rinehart sees the OS-VVM move as important.
“We are helping to make sure that the VHDL community is not abandoned,” Rinehart said in a meeting at DATE this week. “The three large EDA companies have in so many words said SystemVerilog is the foundation of the methodology of choice and that, if you are not deploying it, you need to get on the bandwagon. This opens up legacy issues for VHDL users who are faced with having to reinvest. But we are making the features associated with UVM available through OS-VVM.”