Verilog-AMS release adds to power-aware analog modeling
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
SystemVerilog
Real Intent updates lint tool, adds Matlab and Simulink support
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
Mentor builds simulation-emulation bridge to ‘Verification 3.0’
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
An easier start for UVM, take two
Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.
TVS expands VIP library
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
DAC 2013 Preview IV: Management and Training Days
DAC 2013 will offer a series of dedicated training courses in SystemVerilog, SystemC, and ARM-based design as well as its regular management day bridging the gap between technology and business.
‘Process and metrics before tools for better verification’
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
DATE notebook: Aldec builds in more support for VHDL methodology
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
Synopsys verification IP launch has bite
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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