Mentor cuts scan time in package of test measures for automotive designs
Mentor, a Siemens business, has developed a built-in self-test (BIST) technology that the company claims can speed up the process by an order of magnitude and better support automotive designs that need to perform periodic BIST cycles in running systems.
The observation-scan technology forms part of a slew of announcements aimed at automotive test made at the International Test Conference (ITC) that bring together the various elements of Mentor’s offerings under the banner of the Tessent-software Safety Ecosystem.
Lee Harrison, automotive IC test solutions manager at Mentor, said: “The observation-scan technology is a new approach which helps us make use of each single test cycle. Normally, you perform multiple shift cycles before a capture cycle. With observation-scan we are able to do a capture for every shift cycle. So, with every cycle you are adding test coverage.”
Harrison said the observation-scan approach, which can reduce test times by up to ten times, is made possible partly by a novel scan cell that is used by the LogicBIST engine in combination with changes to the fault-simulation tools used to generation the test sequences. With observation scan, Mentor expects automotive IC designers to be able to perform in-system tests more frequently and so reduce the amount of time it takes to detect a fault while the vehicle is running.
The Safety Ecosystem covers a variety of technologies and tools that Mentor now offers, including the Austemper portfolio acquired earlier in the year, as well as relationships with third parties such as Arm. Under the ecosystem, the Tessent group is building close links to Mentor’s Austemper SafetyScope and KaleidoScope products, which are used to help create fault-tolerant systems. Harrison said the distinction between traditional DFT and fault-tolerance analysis techniques is becoming increasingly blurred in automotive design, with both being instrumental in building safer ICs.
As part of the ecosystem program, Mentor is participating in Arm’s Functional Safety Partnership Program (AFSPP) and has brought IP such as the Cortex-R52 processor under the umbrella. Other offerings in the program are Tessent MemoryBIST and the Tessent MissionMode product, which provides a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system to be tested and diagnosed at any point during a vehicle’s functional operation.
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