June 10, 2016
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
June 30, 2015
Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
October 24, 2014
Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates