DFT to expand its role for long-term yield
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
cell-aware test
Chipmakers see 3x test-pattern saving in embedded-test logic
Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support
Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
PLATINUM SPONSORS
View All Sponsors