Building an RTL sign-off flow
As SoCs become more complex, and the cost of errors grows, it becomes increasingly important that engineers ensure their work is as correct as possible as soon as possible in the design process. They cannot afford to carry errors forward from one stage to the next, where their impact is likely to grow while their causes become obscured.
This requirement is driving a shift in design exploration and hand-off to the register transfer level. Using RTL sign-off eases the integration of heterogeneous IP and makes it easier to check the way that blocks are interfacing with the host design, how clocks will cross these interfaces, power requirements, and testability. It also cuts the simulation load, especially when designs are begin exercised in a system context, which vastly increases the number of states necessary to check functionality.
Initial timing constraints and clocking schemes have to be defined to enable earlier analysis and verification. Power estimation and optimization methods are necessary to provide previews of gate-level performance. The impact of inserting test structures to ease testability has to be considered. There is some good news – working with the design at this level means that each issue can be constrained and addressed by a focused tool, rather than being taken forward to the gate level where they would interact more strongly and hence be more difficult to solve.
What tools are available to improve the quality of RTL code before it reaches the simulation stage? Linting tools have evolved to the point where they can handle full-chip designs of 500 million gates or more, and yet still offer concise reporting. Timing constraints management and checking ensures correct timing for the block and full-chip level, so long as any changes in the RTL are reflected in the SDC files for the design. (The SDC itself needs to be verified for correctness and consistency, and is essential for sign-off grade analyses such as clock design crossing.)
Reset analysis ensures that the design will come in a known good state, and in later iterations of the design may be used to save chip area and routing resources through a more intelligent application of reset signals.
Automatic formal verification techniques can be used to find obscure functional bugs in the RTL, especially in finite state machines, and root out issues, such as bus contention or dead code, which violate the implicit intent of the RTL.
Clock domain crossing analysis, so important in these days of design reuse, IP, and complex power management schemes, can be carried out using a combination of formal and structural methods, which helps trap the corner case combinations of timing and functionality that lead to errors.
Power analysis and optimization techniques address issues such as reset checking, retention flop and isolation-cell analysis and optimization, clock/power gating, and sequential/combinational optimizations. These interventions can be so extensive that it makes sense to go back to the linting stage to recheck the design, and to clear the way for DFT analysis and optimization.
Working at the RTL sign-off level means that even those without DFT expertise can develop DFT strategies and analyze them for the testability that they bring to the design.
As a last step, it is important to manage the way that the simulation and synthesis processes handle the unknown (X) states thrown up by power management strategies that turn blocks on and off, and clocks crossing domains. A proper analysis of this issue can reveal functional bugs that have been hidden at the RTL level by too much optimism about the impact of X states, and reduce the impact of excessive pessimism about the impact of X states after synthesis.
Combining these static verification steps can clean up the RTL and so reduce the simulation burden of testing its function, and the synthesis burden of trying to implement conflicted code. And it means that the design will be as correct as possible as soon as possible, helping meet time to market goals.
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