DFT

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.