DFT

August 7, 2014

NI aims to bring design and production closer with chip-test plan

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
September 9, 2013

SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
May 14, 2013

Real Intent-DeFacTo sign-off flow for RTL combines CDC and DFT

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,

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