National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.
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