Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.
FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Highway1 has opened up Spring applications for its incubation service for hardware startups: trying to overcome the gap between prototype and product.
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
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