DFM

October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
May 24, 2015

Cadence updates Allegro with PCB production and routing tools

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:
April 21, 2015

Cadence updates OrCAD line with additions for PCB manufacturability and integrity

Cadence Design Systems has added five products to its OrCAD line of PCB-design tools that cover manufacturability, signal integrity and management, and introduced three feature updates.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:
July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 27, 2014

Mentor’s Valor tightens PCB design-to-manufacture links

Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Article  |  Topics: Blog Topics, Blog - PCB  |  Tags: , , , ,   |  Organizations:
November 6, 2013

Entrepreneurs get help for hardware

Highway1 has opened up Spring applications for its incubation service for hardware startups: trying to overcome the gap between prototype and product.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , ,   |  Organizations: ,
May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , , , , , ,
October 26, 2012

Mentor Graphics CEO Wally Rhines – Interview

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Article  |  Topics: Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: , , , ,   |  Organizations:
June 4, 2012

DAC 2012: Google your way to DFM

The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
Article  |  Topics: Design to Silicon, Standards  |  Tags: , , , ,   |  Organizations: ,

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