FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Highway1 has opened up Spring applications for its incubation service for hardware startups: trying to overcome the gap between prototype and product.
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Can pattern recognition improve deign rule checking at advanced nodes?
The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]