Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Silicon photonics has been an ‘almost there’ technology for something like a decade. It holds out the prospect of incredibly fast data transmission in a CMOS integration environment. Sounds great. Use a tried and trusted process technology to get a massive performance boost.
But silicon photonics has lacked a critical mass of markets demanding its capabilities and, as a result, the necessary design tool, foundry and test infrastructure to develop profitable products.
Over the course of 2017, that has begun to change.
Photonics leverages the same light communication concepts that have long driven fiber-optic transmissions over backbone networks – and, never mind data centers, we are now at the point where fiber-to-the-home is commonplace. But what about fiber-to-the-chip?
Silicon photonics is about delivering transmission rates within, say, server blades at potentially 1Tbps. That’s fast enough to download a whole day’s UHD athletics coverage from the Olympics in less time than Usain Bolt ran the 100 meters.
As growth in AI, HPC, 5G and the IoT increase the volume of data traffic and decrease permissible latency, established Ethernet-based copper solutions will soon run out of gas. So a major performance argument for silicon photonics has now fallen into place.
Then, consider the move toward autonomous vehicles. A key enabling technology on its sensing side is expected to be LIDAR, which uses pulsed laser light to map a car’s surroundings. A fully self-driving, ‘Level 5’ vehicle is likely to have many LIDAR systems dotted around its body but at current prices that would make the car prohibitively expensive. Integrating LIDAR in CMOS will see those prices drop precipitately. So, the cost argument is in place too.
As the potential silicon photonics market overview in Figure 1 shows, there are other rapidly emerging opportunities in biophotonics (expected to reach a TAM of $19B by the end of the year) and microfluidics (set for a $7.6B TAM by 2021).
Figure 1. Silicon photonics ICs – End market TAM (PhoeniX Software)
By leveraging this potential, the global photonics IC market could grow from around $500M today to $1.3B by 2022, according to Transparency Market Research. Given slower growth prevailing in other semiconductor markets, you can see why people are getting excited.
The Trouble with the Curve
There are however long-standing challenges when it comes to designing photonics ICs that target CMOS. The technology quite literally throws standard tooling a curveball.
The waveguides in photonics are curvilinear structures (Figure 2). Traditional tools and foundry PDKs are constructed for and derived chiefly from an assumption of Manhattan layouts.
Figure 2. Silicon photonics IC layout (Mentor – A Siemens Business)
In addition, the designs are highly sensitive to variations in both process and temperature, and still the field has to settle on a base material. Will it be silicon nitride, indium phosphide, silicon or something else?.
The result is that much of the design work – potentially the greater majority – is carried out by hand. Meanwhile, the DFM feedback loop from foundries is nascent, particularly given low volumes due to the frequent use of multi-project wafers (MPWs) for silicon photonics manufacturing.
Ask any company in the game about yields, and two likely responses are a grimace or a mild expletive. Sometimes, you get both.
Intel is the best-known player in the technology today. It has the internal design capacity and it has the fabs with which to ascend the learning curve and even develop in-house tooling. Based on those resources, it is bringing silicon photonics products to market. Intel, though, is not exactly known for sharing. What about everyone else? What about competition?
Other big companies are interested. Cisco Systems, IBM, Huawei and STMicroelectronics are four of them. Defense research agency DARPA is aggressively funding silicon photonics research, seeding interest in the mil/aero area. However, many analysts point out that they have all been investing for some time with, mostly, little demonstrable return. Moreover, a large part of the market is made up of start-ups working on the tightest of budgets, and targeting applications in what are still emerging segments.
For all its promise, photonics has long been dogged by an image as silicon’s Wild West. To stimulate growth and achieve maturity, it has needed three things.
- Access to greater automation through tooling at reasonable rates.
- Integration between tools, particularly those that target silicon photonics and those that underpin the existing CMOS infrastructure.
- Sufficient foundry volumes to inform fab recipe-making and design-tool layout, DFM and verification capabilities.
Since the beginning of the year, these elements have begun to fall into place.
Silicon photonics tooling cost
A good example of how the tools and foundry markets are moving to stimulate silicon photonics is a recently launched and ongoing collaboration between Mentor – A Siemens Business and Canadian not-for-profit research and commercialization hub CMC Microsystems.
Mentor has Calibre the market leading DFM and physical verification suite for CMOS designs; CMC provides MPW services and has targeted photonics as a particular area of interest.
Under the agreement, CMC’s MPW customers for silicon photonics can get access to Calibre through the Canadian company’s portal free-of-charge for their first two tape-outs. If a customer goes on to a third tape-out, they are asked to purchase a Calibre license. The assumption is that they have reached sufficient maturity and secured significant funding so they should be treated more like a standard EDA customer.
The model is similar to how EDA vendors treat university customers, seeding use of the products. Moreover, the silicon photonics market has a sizeable number of young academic spin-outs in it.
However, what Mentor acknowledges is that it is itself only a certain way along the silicon photonics learning curve – as indeed is the whole EDA industry. This is where the two other elements required will, it is hoped, really satisfy the needs of the design companies and their suppliers.
Silicon photonics tool integration
PhoeniX Software is one of the longest established suppliers of tooling for photonics ICs. Its history goes back roughly a quarter of a century to its launch by researchers at Twente University in the Netherlands, with foundations in photonics for long-haul communications.
Today, its OptoDesigner software is used widely in the silicon photonics market to synthesize circuits based on correct-by-construction algorithms and performance criteria.
Importantly, it does this by a process that is analogous – though not identical – to that for many aspects of traditional silicon design. For example, it has mode solvers that work in much the same way as TCAD does to design a transistor. Its circuit-level operation is similar to a SPICE environment in its construction. This makes OptoDesigner ripe for integration with EDA tools – there’s common philosophical ground.
To that end, Mentor and PhoeniX announced in June the integration of OptoDesigner and the Calibre nm platform.
The integration is shown in more detail in Figure 3, and was described thus:
“The integration enables designers to run Calibre verification directly from the OptoDesigner design tool using the Calibre Interactive invocation GUI, then receive and view the results in OptoDesigner via the Calibre RVE results viewing environment.
“Highlighting, zooming, waiver management and error debugging can be performed through the Calibre RVE interface, while making corrections in OptoDesigner. OptoDesigner can also import the Calibre results directly into the tool, if the designer so desires.”
Figure 3. Calibre-OptoDesigner integration (Mentor/PhoeniX – click to enlarge)
And so another piece falls into place.
Silicon photonics beyond the MPW
The manufacturing feedback loop is crucial to getting the best out of CMOS and it requires a statistically-robust volume of wafers running through the fab. All too often, current silicon photonics designs go through a foundry PDK and come back marked with a massive number of errors, some of them not errors at all – those darned curves again.
To say that the larger chip manufacturers have been resting on their laurels would however be unfair.
GlobalFoundries launched its silicon photonics roadmap in 2016 and moved to Phase 2 – based on a 90nm process run on a 300mm wafer baseline – in Spring. The move to 300mm wafers is significant because the production equipment is more advanced, offering improved bandwidth over 200mm and coping better with rendering waveguides.
At about the same time, specialty foundry TowerJazz announced its own collaboration with PhoeniX to produce PDKs for optical networking and data center designs.
Then, enter the 800lb gorilla. TSMC announced joint development of a silicon photonics platform with Luxtera, one of the market’s most established start-ups and a specialist that is already shipping networking modules. The goal is the full integration of optical interconnects with CMOS logic on SoCs.
These – and other rumored alliances – are the types of deal that will produce the manufacturing and yield data volumes required to inform EDA tools. They also show that the foundries are increasingly convinced that a viable silicon photonics market exists. GlobalFoundries’ commitment extends, for example, to not just a single pilot line but two of its fabs: East Fishkill and Singapore.
If you can build it….
The infrastructure that will allow silicon photonics designs to be realized on a cost-effective basis is coalescing because the applications that will leverage 1Tbps are easy to see.
Moreover, the broadening supply of tools and services looks set to make the market more competitive. Intel deserves kudos for leading the way, but there has long been nagging doubt among some of its potential customers about being locked into a single source.
But there are still challenges to resolve. Back-end packaging and test is a non-trivial concern. For example, if interconnects cannot yet be successfully integrated on a chip – remember that is TSMC and Luxtera’s ‘goal’ – then are we looking at stacked 3D structures or interposers, and one with potentially polymer waveguides sitting on it?
The good news again is that the OSATs have been watching. At Semicon Taiwan, for example, Amkor discussed the work it is already doing both at the chip-on-wafer and system-in-package level.
It looks like the industry has finally seen the light.
