Mentor Graphics CEO Wally Rhines – Interview
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
DFM
The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
DAC 2012: Google your way to DFM
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
Making dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
DATE notebook: Mentor adds pattern recognition to GlobalFoundries’ DRC flow
Can pattern recognition improve deign rule checking at advanced nodes?
ISQED focuses on systems, education and sensors
The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]