Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
Does the internet of things (IoT) require a change in design techniques? A number of people involved in the EDA industry reckon it does.
TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.
Two of the custom designs presented at the 26th Hot Chips in Cupertino exemplified the problems caused by increasing power density and the benefits of looking at heat removal at the system level.
Chinese foundry Semiconductor Manufacturing International Corporation (SMIC) is to get a helping hand to develop a production-class 28nm process from Qualcomm Technologies.
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