At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Freescale Semiconductor has tuned the design of the KL02 microcontroller to produce a new design that is close to 20 per smaller.
Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Memoir Systems has developed a set of memory controller IP cores that exploit common access patterns used by processors in network switches to improve performance and power consumption
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