28nm

June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
June 6, 2014

eSilicon to cut costs of ASIC development for IoT, other markets

Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Article  |  Topics: Design to Silicon, GDSII, Blog - IP  |  Tags: , , , ,
June 2, 2014

Chipmaking’s future: all of the nodes all of the time

The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
May 14, 2014

Samsung agrees to make 28nm FD-SOI

STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations: , ,
April 15, 2014

Common Platform foundry alliance to be wound down

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
March 20, 2014

ADC design shifts gears for lower power

SAR analog-to-digital converters promise better energy efficiency for a growing range of designs, as S3 Group has found.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
February 27, 2014

Freescale tweaks Cortex-M0+ MCU to squeeze die size down

Freescale Semiconductor has tuned the design of the KL02 microcontroller to produce a new design that is close to 20 per smaller.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations:
November 5, 2013

Synopsys aims at fast real-time apps with ARC HS family

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
October 22, 2013

Memory gets smarter for network speedups

Memoir Systems has developed a set of memory controller IP cores that exploit common access patterns used by processors in network switches to improve performance and power consumption
Article  |  Topics: Blog - EDA  |  Tags: , , , ,

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