S3 Group has launched the second in a family of low-power successive-approximation (SAR) ADCs, with a design that supports sample rates up to 320MS/s.
The 12bit ADC is designed for use in communications-oriented designs, such as those based on the 802.11ac and the follow-on 802.11ax WiFi standards as well as higher-speed DSL modems.
Currently designed for the 40nm and 28nm nodes, the converter consumes 10mW and occupies 0.05mm2 of die area. The company’s first foray into high-speed SAR ADCs was a 160MS/s core that takes up 0.1mm2 on a 40nm process.
The company is switching from traditional pipelined ADC architectures to SAR because of its better energy efficiency and improve ability to take advantage of digital scaling.
“Advanced communication standards in the cellular, WiFi and DSL segments, are incorporating spatial diversity techniques that lead to the inclusion of multiple ADCs on single SoCs. Equally as important as the challenge of delivering robust dynamic linearity at higher sample rates, is the need for smaller ADCs that consume less power,” said Darren Hobbs, director of product management for semiconductor solutions at S3.