TSMC adds sub-micron low-leakage processes
TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes.
The new processes add to the existing 0.18µm extremely low leakage (0.18eLL) and 90nm ultra low leakage (90uLL). Supporting processing speeds of up to 1.2GHz in the most advanced version, radio frequency and embedded flash modules are available in the in new 55nm and 40nm technologies.
The foundry said changes to the process can reduce operating voltages by 20 per cent to 30 per cent compared with existing versions. For example, the 55LP process is designed for a typical supply voltage of 1.2V. This drops to 0.9V on the ULP version. The 28ULP drops to 0.7V compared to a typical supply of 0.9V for the 28HPC.
Some early design engagements with customers using 55ULP, 40ULP and 28ULP nodes have been scheduled for 2014. Among the early customers for the ULP option is Bluetooth specialist CSR. with risk production planned in 2015, the 55ULP logic and RF process will qualify ahead of the embedded-flash version.
Joep van Beurden, CSR’s CEO, said: “For many years, CSR has closely collaborated with TSMC, and we are pleased to demonstrate the results of that collaboration with the adoption of the 40ULP platform for our next generation of Bluetooth Smart devices including products for markets like smart home, lighting and wearables.”
Svenn-Tore Larsen, CEO of Nordic Semiconductor, added: “We have been collaborating closely with TSMC on the selection of process technology for our upcoming nRF52 Series of ultra-low power RF SoCs. I am happy to announce that we have selected the TSMC 55ULP platform. This process is a key enabler for us to push the envelope on power consumption, performance and level of integration of the nRF52 Series.”
Cadence Design Systems and Synopsys are among the companies offering IP for the low-leakage processes. Cadence said the company is migrating key elements of its IP portfolio including design IP for memories, interface and analog functions to the technology platforms.
