Imperas and Synopsys team on RISC-V debug
Imperas Software has begun a collaboration with Synopsys that will couple the ImperasDV verification IP with the VCS simulation and Verdi debug engines.
ImperasDV has native support for the open standard RISC-V Verification Interface (RVVI) and uses a ‘lock-step-compare’ co-simulation methodology for processor verification, including asynchronous events and debug operations. This involves co-simulation between the RTL design under test (DUT) and the Imperas RISC-V processor reference model. With the integration, users can move between the custom RTL and Imperas RISC-V reference model using Synopsys Verdi and the Imperas eGui.
“Simulation is the foundation supporting all of the semiconductor industry for design and verification,” said Simon Davidmann, CEO at Imperas . “The Imperas reference models and simulation technology are structured for close integration within co-simulation and emulation environments.”
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