DVCon Europe looks to network effects

By Chris Edwards |  No Comments  |  Posted: November 21, 2022
Topics/Categories: Blog - EDA  |  Tags: , , , , , , ,  | Organizations:

The obvious attraction of any conference lies in the keynotes and technical presentations. But as events return to physical presence and meetings, a conference such as DVCon Europe which takes place in December provides a venue for coordinating the open-source efforts that are becoming an increasingly important part of electronic design automation (EDA) and for bringing together disparate elements of verification into large models that in some cases can act almost as digital twins.

“In the design verification space, we are moving into a multi-dimensional problem, where it’s not only hardware and software, but it’s also how to leverage design technologies, from simulation to rapid prototyping and emulation,” says Martin Barnasconi, who is responsible for global coordination at DVCon Europe and technical director for system design and verification methodologies at NXP. “You’ll notice in some of the submissions [to this year’s DVCon Europe] that people try to move beyond a single solution, a single methodology.”

One element of DVCon Europe that is different to the other DVCons during the year is the SystemC Evolution Day that follows the main conference. Mark Burton, technical program vice chair and principal engineer at Qualcomm, notes, “There, the focus is very much on connecting simulations together and building larger simulations. I think in that domain, we are seeing more and more thought and emphasis going into how different architectures can be used, how different elements of cloud computing can be used, either [on-premises] cloud or public cloud, and not just for verification of hardware, but also software verification. So this is this is verification up the entire stack, if you will.

“Last year, there was an interesting paper on integrating FPGA with SystemC models. This year, there’s some interest in various different simulators, including QEMU,” Burton adds.

Open-source interaction

The steady increase in the use of open-source tools, coupled with the use of Python to integrate many of them, calls for much greater interaction within the industry. A panel at the Design Automation Conference (DAC) underlined the importance not of creating open-source components and forks but their ongoing maintenance and community support.

Andreas Olofsson, head of Zero ASIC who while heading up one of DARPA’s groups was responsible for setting up the project that led to the open-source OpenRoad implementation flow, pointed out at the July conference that they require “checking in for the long road: there is a lifetime of open-source maintenance”. However, that does not mean one person’s lifetime: critical mass is vital, so that a community of people can work together to build useful tools that do not just tackle one specific user’s problem.

“Open source is all nice, but it we should also be careful, because a project might be successful for a few years but then the key designer leaves. And then the GitHub repository remains unmaintained,” says Barnasconi.

Burton adds, “One of the nice things of DVcon is that we meet people and we can understand what their comfort zone is and what their expertise is. And find out the people who are willing to work together as a community to help maintain a library.

“The response we often get is that people say, ‘Oh, no, no, but I’m not an expert like you guys. I’m just a beginner’. That doesn’t matter. Everybody is welcome. We are willing to onboard people who are not, let’s say, an expert in UVM, or in SystemC. With events like this, we can also see if we can scout for people who are willing to keep the ball rolling.

“Open source provides the ability for people to find an itch and scratch it. I think that’s the advantage that you get from open source. I don’t think the advantage is necessarily the price or anything like that. I think it’s much more about the ability of standing on somebody else’s shoulders and adding to it,” Burton says.

The other ingredient lies in standardization, Barnasconi notes, “Is there a common infrastructure? Is it supported by an ecosystem. Only open source will not save the day, we also need open standards as an ingredient. And that’s why some of us are very active in Accellera.”

ML’s continuing rise

Another key trend, again supported by open-source infrastructures such as PyTorch as well as the commercial offerings that are aimed at EDA, is the use of and machine learning (ML) in verification. Cooperation here is likely to be key to driving this technology forward in verification, though it will take some time.

“We are seeing movement towards ML-drive verification, but not really converting this into substantial standard development process yet,” says Sumit Jha, DVCon Europe general chair and senior staff engineering manager at Qualcomm. “I think the reason is that AI/ML is heavily dependent on data. And the data around these is very much company specific in a situation where companies are sensitive about sharing this data. So, in order to come up with a standard solution, it’s a little bit hard in this department. But we are certainly seeing a shift towards the use of AI and ML more and more in verification.”

Python is becoming the glue for bringing these tools together. Burton points to work where the interpreted language has been used for implementing tests that involve fault injection. “And there are indeed papers that are talking about machine learning and using Python for that,” he says, adding that the language has useful tools for not just for implementing functions but performing pre- and post-processing and visualization of the results.

“It is gaining more traction,” says Barnasconi, “Some EDA vendors are now even suggesting or proposing extensions and embedding Python in their commercial offerings.”

In turn, these infrastructures provide the ability to tackle the challenges of building very large complex systems such as those covered in the two DVCon keynotes this year: one focuses on the verification of 5G and 6G radio; the other on the mix of hardware and software now going into automotive design.

DVCon Europe takes place in Munich, Germany on December 6th and 7th, 2022, and is followed by the SystemC Evolution Day.

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