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Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium

Manufacturability, routing, library design and more - it all needs rethinking at 20nm

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).



With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.

Designers should plan ahead for future process changes as conventional silicon CMOS runs out of steam, IMEC's Rudy Lauwereins told delegates at the International Electronics Forum in Bratislava this week.

The semiconductor industry is reaching a crunch point at which companies that form it have to work together much more closely, says Malcolm Penn of Future Horizons.

Open-source hardware is going to change the way people buy computing capacity for data centers, says LSI's Rob Ober

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering.