Blog Topics

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.

Expose your transaction-level innovations to the real world early on and catch bugs before simulation.

All our news and coverage from DAC 2012 is brought together here. Updates throughout the show.

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.

If you're planning your DAC visit or want to set some Google Alerts for next week, it's time to consult the perennial touchstone.

But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes

UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.

The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata