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Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM

EUV sources currently deliver around 10 to 15W, but need to be delivering 200W to make them cost effective for production use. Can the industry boost source power by 2014, or are we stuck with slower scaling?

The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.

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Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium

Manufacturability, routing, library design and more - it all needs rethinking at 20nm

Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.

TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).



With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.