Blog Topics

Samsung Electronics is setting up a center in Silicon Valley to try to develop technologies that the company hopes will ultimately drive volume for its chipmaking operation.

The scope of the Low-Latency Interface (LLI) developed by the MIPI Alliance is expanding as it heads towards version 2 – increasing the ways in which a single DRAM array can be shared between SoCs in a mobile phone.

Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.

GlobalFoundries has confirmed its 14nm process as the one that will see the foundry introduced finFET-based transistors, claiming that its approach is optimized for mobile devices

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

Anyone still tempted to regard PCB design as electronics’ sleepy backwater, obviously hasn’t been taking notice of trends not just in shrinking form factors but also I/O and memory standards. Proliferation not just in standards but in speeds have been creating whole new sets of challenges ranging from power and signal integrity right through to […]

It’s not that long since ARM was, to be blunt, rather fussy about the companies to which it licensed its technology – and at what level. Today, ‘ARM in a box’ comes in a number of flavors. Somewhat appropriately, the company linked with Cadence Design Systems and TSMC at the former’s recent CDNLive user conference […]

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.