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It’s not that long since ARM was, to be blunt, rather fussy about the companies to which it licensed its technology – and at what level. Today, ‘ARM in a box’ comes in a number of flavors. Somewhat appropriately, the company linked with Cadence Design Systems and TSMC at the former’s recent CDNLive user conference […]

The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.

Xilinx says it has made the first public release of its Vivado Design Suite – the reworked design environment for its sub-40mn programmable-logic devices that is based more heavily on concepts from the custom-IC world than its existing ISE toolset.

Characterizing standard-cell defect mechanisms helps improve IC testing

MEMS relay-based devices offer the ultimate in subthreshold leakage: they don't have any. Design and technology advances are promising to overcome problems with reliability, design and speed, according to Tsu-Jae King Liu of UC Berkeley.

During his CEDA talk at DAC last week Professor Mark Horowitz challenged the audience to find holes in the approach he and his team have been developing over the past few years to rethink analog design.

FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.

Cognovo is running a webinar next week (19 June) on model-driven design for software-defined wireless modems.

A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.

Expose your transaction-level innovations to the real world early on and catch bugs before simulation.