IEF: Achronix plans embedded FPGA push

By Chris Edwards |  No Comments  |  Posted: October 4, 2012
Topics/Categories: Conferences, Design to Silicon, Blog - EDA, - General  |  Tags: , , , ,  | Organizations: , ,

Achronix plans to use the FPGA fabric that it has developed for standalone products to be fabbed through Intel as the springboard for an embedded-FPGA offering that it hopes to sell to chipmakers as a way of making their designs more flexible.

John Lofton Holt, chairman of Achronix, explained at the International Electronics Forum today in Bratislava that the technology has shifted far enough in the company’s view to make embedded FPGA, at last, commercially viable. He said the company is not yet in a position to talk about customer engagements but that design work had started and test chips have been taped out for TSMC’s 28nm process – although the focus is on 22nm and below. Assuming the projects run to completion, Holt said volume product of SoCs with embedded-FPGA fabric would be expected in 2014.

Holt said the company had explored options such as multidie packages and 3DIC but that these remain too expensive in the short term to be viable. “We see 3D as being important but not solving any problems for the next two generations,” he said. “Die-level integration is probably the best way to get to the cost problem.”

There have been long-standing problems with embedded FPGA, Holt conceded. “When you talk to customers, they say ‘how much logic can you get in how much die area?’ It usually ends up being most of the device. That was true in 90nm and 65nm and in 45nm. But it’s not true now. It is purely driven by the evolution of process technology. At 22nm, we can do a quarter million LUTs – which is equivalent to a million ASIC gates – in 45 square millimetres.

“We view one million gates as the maximum size that is reasonable for a [SoC] customer,” Holt claimed.

Because the applications that Achronix is looking at are logic rather than datapath dominated, the target speeds are likely to be lower than those anticipated for standalone FPGAs. This could help with the integration by improving routability through the programmable-logic blocks and allowing energy optimizations.

Holt said in most engagements, the fabric would generally be customized in terms of the programmable elements that are used and in layout.

“One big IDM customer only needs a performance of 300MHz, so we can do speed/power tradeoffs. Speed is not a driver: it’s power first, cost second in many of these cases.”

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