Using verification IP to master AMBA and wider protocol proliferation
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
Blog Topics
Board-level DRC tool to find signal-integrity problems
Mentor Graphics has added to its HyperLynx suite a tool that uses design-rule check (DRC) techniques rather than simulation to look for potential signal-integrity problems.
Tile-based integration of analog functions enables power controller family
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
ST aims to seed more interest in FD-SOI
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
FinFETs face planar fightback at IEDM
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
imec ITF: EUV source power woes threaten Moore’s Law scaling
EUV sources currently deliver around 10 to 15W, but need to be delivering 200W to make them cost effective for production use. Can the industry boost source power by 2014, or are we stuck with slower scaling?
OMG adopts portable image and signal processing libraries
The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.
Tech Design Forum moves to new social media homes
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