Mentor extends Questa with formal coverage checks
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
Blog Topics
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
FinFETs face planar fightback at IEDM
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
imec ITF: EUV source power woes threaten Moore’s Law scaling
EUV sources currently deliver around 10 to 15W, but need to be delivering 200W to make them cost effective for production use. Can the industry boost source power by 2014, or are we stuck with slower scaling?
OMG adopts portable image and signal processing libraries
The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.
Tech Design Forum moves to new social media homes
Check out our new pages on Twitter, LinkedIn and Facebook
Intel, TSMC finFETs to star at IEDM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Is your 20nm process gate-last? Maybe it should be
Modelling work by Gold Standard Simulations indicates that gate-last is the sensible choice at 20nm from a design point of view because of variability problems with gate-first processes.
TSMC updates reference flows for 20nm and CoWoS
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
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