October 30, 2012
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
October 26, 2012
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
October 25, 2012
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
October 25, 2012
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
October 25, 2012
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
October 24, 2012
Mentor Graphics has added to its HyperLynx suite a tool that uses design-rule check (DRC) techniques rather than simulation to look for potential signal-integrity problems.
October 24, 2012
Using a tile-based analog design methodology to produce power application controller ICs at Active-Semi
October 18, 2012
STMicroelectronics offers 28nm process to smaller scale users through CMP and Soitec
October 17, 2012
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
October 16, 2012
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology