Using verification IP to master AMBA and wider protocol proliferation

By Paul Dempsey |  1 Comment  |  Posted: October 25, 2012
Topics/Categories: Blog Topics, Commentary, Blog - EDA, - Standards, Verification  |  Tags: ,  | Organizations: , , ,

Success stories are what they are. The ones that catch your attention are backed up with user experience. So, two of the three ARM AMBA verification IP examples that Cadence Design Systems has announced may merit your further investigation. They involve Hisilicon and CEVA.

Both come from ‘best paper’ presentations previously available only to attendees at editions of the company’s CDN Live user conference in respectively China and Israel. Both involve aspects of an AMBA protocol family so common in the mobile space and for which ARM has ambitions in the server market (remind me who launches a 64bit flavor of its architecture next week).

Hisilicon and ACE verification IP

First, the experiences of Hisilicon, the Huawei subsidiary. It was working with the ACE (AXI Coherency Extensions) protocol added to AMBA4 last year. It addresses cache coherency for multicore designs. ACE aims to ensure that each core operates on the most up-to-date data, regardless of where it resides (that core’s own cache, another core’s cache, or main memory). It also comes with the low-power hallmark associated with ARM. So, better reliability, better energy, better performance.

Problem is ACE is a bit of a beast. The documentation runs to 300 pages. The verification effort must cover multicore communication, 17 ACE commands, five cache states,  and simultaneous transactions in different channels. The cache state is hard to predict, certainly if you are coming to it relatively fresh. ARM provides the CCI-400 Cache Coherent Interconnect design reference. But like all references, it is a starting point. Chances are you will want to differentiate your design beyond that.

(As a side point, Cadence’s Mirit Fromovich has written a very useful overview of the ACE verification challenge for Chip Estimate)

So Hisilicon turned to Cadence to provide the necessary verification IP. Some of the criteria it used were familiar enough: maturity of the VIP and the provider, SystemVerilog and VMM methodology support, access to technical support. But there are wider issues that illustrate general trends in verification IP.

  • Resources – Hisilicon has Huawei behind it but it still faces the problem of not only maintaining in-house knowledge on discrete but complex IP blocks like ACE, but also managing the general proliferation of IP.
  • Verification time – Better more feature-rich IP makes for better chips, but it also boosts test cases and coverage points. Compared to CCI-400, Hisilicon first estimated that the verification effort for its target design would be one whole order of magnitude greater.

So, it hired a supplier that could address those concerns, leveraging a third-party resource that would cut time-to-market. That’s what you always want to do, but the expectations upon those suppliers have grown: Where previously users would have a relatively detailed overview of a protocol but want the finesse in the actual verification IP’s execution, they now need much of that inside knowledge to come from outside.

CEVA and AXI4 verification IP

The second case study involves the Israeli DSP and platform specialist CEVA and its work on customizing the AMBA AXI4 for its proprietary  fabric interconnect configuration (FIC) bus. A more broadly familiar block-level verification challenge, on the face of it. But, as with Huawei, a key issue was again resources.

It took Cadence verification IP because its team were not protocol experts. CEVA has better things for them to do. And it cut its verification time from six months to three weeks.

The customer is looking for knowledge within the verification IP, and not just to say ‘yes’ or ‘no’ to aspects of the design, but to offer a range of options and consequences through the interface.

Meanwhile, getting the product out becomes as much about what you can afford not to know as what you need to know. The difference may be that this balance no longer applies just to those things that are not at the cutting edge.

For sure, Cadence is not alone in looking to make more of both its verification IP and background experience roles. The same capability is a big part of Synopsys’ current push to boost its share of the market, and challenge Cadence’s leadership. The same applies to most other suppliers, particularly boutique players. But instances like these do make the direction clear.

There is a growing pile of standards to manage. Like AMBA, MIPI seems to adds standards and options almost monthly. USB and PCI Express are relentless. HDMI will sprout a 2.0 version later this year. The need to pull on big – or at least experienced – verification IP suppliers who can help you manage the gushing spigot is self-evident.

Meanwhile, you can go inside Cadence’s AMBA VIP offerings here.

Also, don’t miss our interview with Cadence’s Susan Peterson, reviewing many of the trends here.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors