Board-level DRC tool to find signal-integrity problems

By Chris Edwards |  No Comments  |  Posted: October 24, 2012
Topics/Categories: Blog - PCB  |  Tags: , ,  | Organizations:

Mentor Graphics has added to its HyperLynx suite a tool that uses design-rule check (DRC) techniques rather than simulation to look for potential signal-integrity problems.

HyperLynx DRC uses customizable rules to highlight potential design issues that may cause problems with signal integrity, power integrity, and electromagnetic interference (EMI) without simulation.

Sony Mobile, based in Lund, Sweden, has been using the tool for mobile-phone designs. “By using HyperLynx DRC we get a structured approach where all nets are equally checked by the tool. We can then focus the review meeting on the critical nets where the tool finds the violations,” said Anders Olsson, senior manager, Lund Development–Electronics System Design at Sony Mobile. “Valuable time can thus be spent on problem solving instead of problem finding.”

HyperLynx DRC comes with a standard set of coded rules targeted at PCB layout practices that have the potential to cause issues common in high-speed design. These standard rules are parametrically driven so users can customize them to meet internal best practices of their company.

Rules include nets near board edges, coupling to I/O net, interconnects that may be too long or traces that may experience impedance variations or crosstalk issues. Users create and modify rules using VBScript or Javascript.

“Sometimes simulation is not the optimum approach to look for problems, and HyperLynx DRC is targeted exactly for those situations,” stated Dave Kohlmeier, director of analysis products, at the Mentor Graphics systems design division.

HyperLynx DRC works with the major PCB layout tools including Mentor’s Expedition Enterprise, Board Station and PADS, as well as Cadence Design Systems’ Allegro and Zuken’s CR.

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