imec ITF: EUV source power woes threaten Moore’s Law scaling

By Luke Collins |  No Comments  |  Posted: October 15, 2012
Topics/Categories: Blog Topics  |  Tags:

Continuing difficulties in raising the output power of EUV sources are threatening to slow the scaling of IC manufacturing processes, according to speakers at imec‘s International Technology  Forum in Leuven, Belgium  earlier in the month.

EUV has to succeed because if it doesn’t then this industry will have  a big problem,” said Luc van den Hove, imec president and CEO. “Scaling will drastically slow down if EUV is not available.”

He added that although the organisation is seeing steady improvements in source power “progress there is considerably slower than people had expected five years ago.”

The result has been a shift to more gridded design styles to enable the use of double patterning (Guide) with 193nm optical lithography, as well as research into directed self-assembly techniques that rely on using two block co-polymers of different lengths to form narrow line/space patterns in relatively broad channels created by conventional lithographic techniques.

Although this directed self-assembly approach may work well as an alternative to double patterning for very regular structures, Van den hove pointed out that users will still need EUV lithography for the cut masks that divide up the patterned lines into the cell layouts.

“For 14nm processes,” Van den hove added, “you need EUV, otherwise you have to modify the design rules and lose density.”

The problem is, EUV source power remains an issue.

According to Kurt Ronse, director of the advanced lithography program, imec took delivery of the latest ASML preproduction EUV stepper, the NXE:3100, and its Ushio source, in October 2011 and it has been less than smooth sailing since.

“We have had some weeks which were very good and some that were very bad and as a result the average uptime never reached 50% and was sometimes closer to 30%.”

A source upgrade in March has improved uptime to between 70 and 80%, but the 20W source has only been run at up to 9W to date.

Ronse says that using the AMSL tool and chemically amplified resists it is possible to produce patterns with 16nm half pitch, Unfortunately these resists take more than twice the exposure dose of conventional resists “which is putting more pressure on the source manufacturers.”

A recent symposium on EUV organised in Brussels by imec concluded that the industry would be able to offer 200W sources in 2014.

“The conclusion today is that there is still a big gap,” said Ronse. “Source powers today are 10 to 15W – that is seen as the biggest challenge.”

To use the chemically amplified resists that enable the densest patterns, the Symposium concluded that the industry would need source powers of 500 to 1000W by 2016.

“The positive is that in the past 12 months we have seen real reliability improvements,” said Ronse, “but for power we still have a long way to go.”

Ronse concluded: “Next year EUV is not going to start production so people will use 193nm lithography with multiple patterning.”

There will be an impact on cost and results to using this approach.

“Design rules are being relaxed to enable the use of double patterning and area scaling is no longer 50% going from 20nm to 14nm,” said Ronse. “It is going to be very expensive and  very time consuming to use multi-patterning.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors