Blog Topics

New MicReD power tester identifies failure causes without the need for post-test lab analysis

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype

Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.

Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.

Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.

ARM has decided to shift from using its in-house compiler technology to the open-source combination of Clang and LLVM.

The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.