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Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.

STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.

New MicReD power tester identifies failure causes without the need for post-test lab analysis

HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype

Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.

Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.

The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.