EDA

Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.

Siemens has refreshed its collaboration with PDF Solutions with the aim of using test data and other sources to provide actionable information to improve device yield.

Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.

The design and verification IP specialist will present its full range, including the Smart Compiler, at next week's Design Automation Conference.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.