DAC 2013 Preview IX: Manufacturability
With the manufacturability and yield of processes at 20nm and below still largely an unknown quantity, interest in manufacturability and related issues will be running high at this year’s DAC. Here are some of the key sessions on manufacturability and related issues that we have spotted in the conference schedule.
Monday, June 3, 2013
Winning in Monte Carlo: Managing Simulations Under Variability and Reliability
Three sessions: 11AM – 1PM, 2 – 4PM, 5 – 7PM, tutorial, 13AB
This session looks at ways to manage the increasing variability and reliability issues, and hence the growing verification burden, caused by moving to finFET devices. The session will include a look at CAD and circuit techniques for variability and reliability; an analysis of the different ways in which variability and aging affect bulk and finFET device performance; and a discussion of new approaches to verification. There will also be a case study from nVidia on maintaining signal integrity using variation-aware design techniques.
Tuesday, June 3, 2013
The Many Faces Of Advanced Technology
11:30AM – 1:30PM, Hilton Grand Ballroom H
Synopsys has gathered experts from foundry, processor, wireless and consumer electronics companies to talk over lunch about they way in which they have used new place-and-route tools to address design challenges including: working with finFET processes; taping out a complex SoC at established nodes; and achieving gigahertz clock speeds.
Don’t Fret About Your FinFet: Physical Design in 14nm and Beyond
Time: 1:30 – 3:00 PM, paper session, Room 14
This session covers a lot of manufacturability related issues, including: an analytic framework for assessing finFET based technology nodes; how to route a chip so that it can be made using multiple e-beam lithography; and automatic design rule correction in the presence of multiple grids and track patterns. There is also a paper on planning multiple chips for use in a 3DIC based on an interposer.
Designer Track: Poster Session 1
12noon – 1:30PM, Hall 5
It might be worth seeking out this session for an intriguing looking poster from IBM and the Silicon Integration Initiative, entitled QA Flows for DFM using Open Standards.
DAC Management Day
10:30 – 4:30 PM, Room 17AB
Since manufacturability is such a far-reaching topic, it may be worth spending time at DAC’s Management Day, where senior managers from fables and fab-lite companies, systems houses and suppliers will discuss making the trade-offs necessary between manufacturability, power consumption and die are at advanced nodes. Two sessions will discuss these changing needs and present corresponding management decision criteria for making the right choices from a pool of alternate options for flows, methodologies, and suppliers.
Wednesday, June 5, 2013
Litho is hot
9:00 – 10:30AM, Room 14
This session will discuss advances in lithography. Topics include: hot-spot detection; an efficient way to decompose a layout for triple patterning; and a paper that discusses ways to overcome the throughput limitations inherent in using overlapping stencils in electron beam lithography.
12:00 PM — 1:30 PM, Hall 5
A number of papers catch the eye in this session:
7.38 – Turning Failures into Dollars: Results of a Volume Diagnostic Analysis Pilot, from Freescale Semiconductor
7.40 – Placement Dependent Variability Assessment of Standard Cell Libraries, from LSI Logic
7.43 – Automatic Generation of DFM Via Definitions, from Freescale Semiconductor
7.51 — Pioneering an On-the-Fly Simulation Technique for the Detection of Layout-Dependent Effects During IC Design Phase, from Mentor Graphics
Learn the Secrets of Design for Yield
1:30 PM – 2:15 PM, Pavilion Panel, Booth 509
This panel will discuss ways to counter the yield impact of increased device variability at advanced nodes through a better understanding of device modeling. Panelists are from SMIC, TSMC, and GLOBALFOUNDRIES.
Physical Design and Manufacturability
4:00PM – 6:00PM, Designer Track, Room 18C
This session will include presentations covering: a flow to reduce hotspots; a hierarchical methodology for very high-frequency microprocessor designs; power distribution and clock-tree synthesis for large low-power ASIC chips, a flow to handle clock-domain crossing logics; and a top-down flow for 3D-IC designs.
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