Siemens pushes DRC to the left
Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Siemens EDA
Siemens compiles analog into simulation for faster debug
Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.
Fujimura asks EDA to bend towards manufacturability
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
Coherency verification for CXL
CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.
TSMC certifies Aprisa for N5 and N4
TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.
Siemens brings ReadyStart RTOS to RISC-V
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Navigate variables and lifetimes in SystemVerilog
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Go inside proposals for common chiplet models
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
Verifying the new namespace storage options in NVMe 2.0
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Learn strategies for better measurement and test in simulation-based PCB design
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
PLATINUM SPONSORS
View All Sponsors