RFICs are not different from most other parts of chip design in having moved toward greater system-on-chip level integration, and as they have simulation budgets have been pushed to the limit.
A new technical article explores how teams can use a combination of EDA and early verification strategies to mitigate the demands ultimately placed on computationally expensive and time-consuming simulation.
For designs that now tend to position ADCs, DACs, PLLs and more on the same die as the RF front-end, it reviews how to address the challenges that arise in four areas:
- Design topology checking – requiring the observation of foundry and internal rules as well as device selection and hard to achieve manually.
- RF/analog layout checking – with particular regard to the importance of catching layout-dependent effects before that can potentially slip right through to silicon.
- Shallow trench isolation and well proximity effects – problems that can affect mobility, threshold voltage and promote rapid degradation.
- RF/analog layout fill insertion – fill can help in many ways but wrongly implemented can again lead to degradation, capacitance delay and other effects.
The paper provides a number of tips and techniques for catching issues in these areas early so that simulation runs can be optimized. It does so with particular reference to a number of tools in the Calibre family from Mentor, a Siemens business, including Calibre PERC, Calibre YieldEnhancer and Calibre Pattern Matching.
‘Improving the reliability and performance of RFICs with advanced EDA technology‘ is available from this link.