Cloud access to emulator helps AI processor start-up prove design, win funding

By Luke Collins |  No Comments  |  Posted: August 27, 2020
Topics/Categories: Blog - EDA, - Product  |  Tags: , ,  | Organizations:

AI chip start-up SimpleMachines (SM) has used cloud-based access to Mentor hardware emulators to validate a cycle-accurate model of its first processor, verify its RTL, and demonstrate the merits of its architecture a year before first silicon was due. The approach helped SM secure the funding needed to complete the chip.

SM’s AI processor uses a ‘composable computing’ approach that implements multiple processor subsystem blocks and a complex switch fabric on a chip. These can then be configured to accommodate evolving software workloads. This ability to match hardware resources to software needs is claimed to increase the power efficiency of the chip, as well as giving it a degree of future-proofing by enabling the processor to adapt to emerging AI and machine-learning algorithms.

SM turned to Mentor, a Siemens company, for access to its Enterprise Verification Platform, including the Questa simulator, Veloce Strato emulator, and Questa verification IP for PCIe and HBM2 interfaces. It accessed the emulator through Mentor Consulting’s cloud-enabled Emulation-as-a-Service (EaaS) offering. The consulting team helped SM move its design onto the emulator, dealing with emulation-specific issues such as the modelling of non-synthesisable logic, memories, caches, and analogue interfaces.

The result was a cycle-accurate model of the design expressed in RTL running on the emulator, which SM could then use to test its processor configuration and management software and some of the architectures it was intended to instantiate. It was this approach that enabled SM to show a potential client the validity of its approach, even as the RTL of the design was still evolving.

Mentor Consulting also helped the SM design team by implementing power-analysis capabilities on the processor design, so that SM could then probe the RTL to understand which areas of the chip would contribute most to overall power consumption.

“We needed a cycle-accurate model of our hardware very early in the design and development phases of our first-generation device,” said Karu Sankaralingam, CEO for SM.

“We turned to Mentor Consulting’s exceptional simulation/emulation flow, together with the sound expertise of Mentor’s consultancy services, which allowed us to port our neural network software to the underlying hardware much faster than we expected. Mentor’s EaaS played a critical role in enabling us to rapidly develop and differentiate our AI system software a full year before initial availability of first silicon.”

Mentor’s EaaS provides customers with secure and reliable access to the cloud-hosted Veloce emulation hardware platform without requiring ownership or management of an emulator and associated infrastructure. The service includes expert consulting, which SM used to cut the costs and speed up the process of using the Veloce emulator.

For years, customers have been able to put their designs onto secure servers in Mentor facilities in order to get help with working the tools or exploring debug issues. This offering has now been expanded to include remote access to hardware emulation. Under this approach, Mentor establishes a secure Linux host in a cage at one of its facilities and uses it to host its emulation and debugging software. The secure host accesses the emulator through another server, and is accessed by the customer over a secure communications channel and remote desktop software. Customers can then compile code, launch emulation jobs, debug and edit their designs using the remote desktop, before transferring the completed design back to their premises over the secure channel.

John Anderson, verification consulting manager at Mentor, said: “For small companies, an emulator can mean a big investment in capital, facilities, support, maintenance and so on. Our EaaS approach gives flexibility in time and capacity.”

Anderson estimates that a design can often be ported to an emulator within one or two months, which compares with a typical six-month cycle to build an FPGA prototype, or up to a year to get first silicon.

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