Integration forms highlights of upcoming IEDM
Different forms of heterogeneous integration take center stage at the IEEE International Electron Device Meeting (IEDM) in December this year.
IMEC
The road to ES Design West: Location, location, location
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
IEDM shows progress on embedded eMRAM
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
IEDM to examine scaling from multiple directions
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
Imec stacks transistors for denser 3nm option
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
Switch to orbit mode boosts MRAM on 300mm wafers
Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
Pillar transistor points to smaller SRAMs at 5nm
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Cadence and Imec tape out 3nm interconnect test chip
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.