EDA

February 20, 2018

DVCon US 2018 preview: OneSpin Solutions

The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
February 16, 2018

SPIE Advanced Lithography 2018 preview: Mentor

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , , , , ,   |  Organizations: ,
February 15, 2018

DVCon US 2018 preview: Oski Technology

The formal verification specialist will be discussing its own experiences and has partnered with users for presentations at DVCon US.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: ,   |  Organizations: ,
February 14, 2018

DVCon US 2018 preview: Breker Verification Systems

Breker's work towards the portable stimulus roll-out will lead much of its offering later this month in San Jose.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations: ,
February 13, 2018

HyperLynx update automates SerDes validation

Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Article  |  Topics: Blog Topics, Blog - PCB, - Product  |  Tags: , , , , , ,   |  Organizations:
February 12, 2018

DVCon US 2018 preview: Mentor

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
February 1, 2018

Metrics introduces elastic compute to handle peak-time verification

Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
January 31, 2018

Analog blocks go digital for faster integration

Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
January 23, 2018

ARM DesignStart case study demonstrates scheme’s ease-of-use

ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.