EDA

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.

The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.

Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.

With the aim of making it easier for embedded devices to cooperate in an IoT environment, Mentor has launched a cloud connectivity and management framework.

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.