Cadence updates Allegro and Orcad

By Chris Edwards |  2 Comments  |  Posted: September 26, 2012
Topics/Categories: Digital/analog implementation, Blog - EDA, PCB  |  Tags: , , , , , ,  | Organizations:

Cadence Design Systems has updated both of its printed circuit board (PCB) tools – Allegro and Orcad – to improve their handling of design constraints, multiuser design and deal with embedded components and mechanical CAD tools.

Allegro already supports multiuser design through integration with product lifecycle management tools but Cadence has decided to create a more lightweight alternative to make it easier to check pieces of a design in and out. Because Microsoft’s Sharepoint is already widely used by large organization in other areas, Cadence chose that as the platform for the new approach.

Hemant Shah, product marketing director at Cadence, said: “Sharepoint allows block-level check-in and check-out. It provides something that PLM systems don’t provide: with those they have to check out the entire tarball.”

PLM and Sharepoint-based design can be used on the same project. Typically, PCB designers will access pieces of a project under Sharepoint and when they are finished, those designs can be checked out under the PLM system as a whole, often by the mechanical design team who will look at the design’s physical features and other aspects such as heatflow.

For exchanging data with MCAD tools, the company has decided to support the EDMD schema developed as part of the ProStep iVIP standard – choosing a similar approach to that used by Mentor Graphics so far to exchange PCB data with tools such as PTC’s Pro/Engineer and Dassault’s Catia.

The constraints management system has been extended through an addition Cadence calls Auto-interactive Delay Tuning (AiDT). The function automates the job of tuning the length of traces on high-speed buses such as DDR3 so that they have the same propagation delay. Traditionally, the designer has had to do the tuning by hand or individually set the lanes to a specific delay. With AiDT, the designer selects the related bitlanes or bus lines and requests they be matched using a contextual menu.

Through a linkup with EMA’s Timing Designer, constraints for bus and other interfaces can be imported from that tool automatically. Today, Shah said the interface is based on passing text files into Allegro but there are plans to make the exchange between Timing Designer and Allegro more interactive over time.

On the Orcad side, Cadence has made it possible for constraints to be passed backwards and forwards between the schematic editor and the layout tool. This allows the results of early layouts for feasibility and timing to be kept for later use and for the designer to tag I/O lines with constraints to be fed-forward into subsequent layouts.

For embedded components, Allegro now has support for dual-sided contacts and vertically mounted components such as power-FETs.

“Customers are doing some things that took us by surprise. Dual-side contacts? We didn’t anticipate those. They are being used for flexibility of routing but I could also see redundancy being good for applications in areas such as aerospace,” said Shah.

Product marketing director Josh Moore said one of the big additions to Orcad is an expansion of its support for Tcl scripting, particularly for PSpice simulations. “Customers can do things in PSpice they could not do before. You can work with custom equations or substitute variables on the fly that take account, for example, of changes in temperature.”

To improve the performance of analog simulations, the company has made the PSpice simulator multicore-aware so that it can distribute work across the processors in a workstation.

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