Standards

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.

Imperas Software has published an open-source functional-coverage library for RISC-V cores.

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.

Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.

DAC returns to San Francisco in July for its 59th year as a purely in-person event.