Standards

The 70th annual IEDM is putting together its next conference under the theme under the theme “shaping tomorrow’s semiconductor technology”.

This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

Mil/aero specialist Abaco Systems refined its workflow across multiple design sites after the pandemic constrained collaboration.

DVCon Europe is looking for papers to be presented at this year’s event in mid-October.

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.

The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.

Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.