Standards

November 21, 2022

DVCon Europe looks to network effects

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations:
October 25, 2022

DVCon Europe keynotes focus on connectivity

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022

Accellera attempts to standardize CDC data

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Article  |  Topics: Blog Topics, Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
May 23, 2022

IEDM to celebrate 75 years of the transistor

Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
May 5, 2022

DAC returns to SF for in-person event

DAC returns to San Francisco in July for its 59th year as a purely in-person event.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
April 29, 2022

Navigate variables and lifetimes in SystemVerilog

Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations: ,
April 28, 2022

DVCon Europe returns to live format

DVCon Europe will be held as a live event in Munich in early December.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations:
April 28, 2022

Go inside proposals for common chiplet models

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.

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