Cadence joins the dots for verification

By Paul Dempsey |  No Comments  |  Posted: May 16, 2012
Topics/Categories: Blog Topics  |  Tags: , ,  | Organizations:

Joined-up thinking. We hear the term a lot, but when examples of it turn up in the real world, they often don’t get the credit they deserve. So it could initially prove with Cadence’s new look System Development Suite.

After all, a lot of its raw components look familiar. Incisive and Palladium XP are recognized verification environments. Both the Virtual System Platform and the Rapid Prototyping Platform have also now been around for a while.

But the important thing here is the combination of acceleration (there’s both in-circuit acceleration and more accelerated VIP in the new package) and integration across the SDS’ components.

So, where once upon a time you needed separately maintained environments for in-circuit emulation and RTL simulation, the SDS allows you to work with just one. Indeed, the idea is to bring some uniformity through the chain across virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping.

VIP is also becoming one of this year’s battlegrounds. The Cadence Accelerated VIP catalog has been tailored for compatibility across the SDS and now includes a clutch of the most common interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.

Faster and more efficient, up to 10X, Cadence claimed this week. “A single heterogeneous environment for system-level verification.”

We’ll be going into more detail about the suite in the next few days. Stay tuned.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors