Even as 28nm digital processes start to settle down, fabs and tool vendors are starting to discuss their work on bringing analog and mixed-signal (AMS) capabilites to 20nm processes.
STMicroelectronics and Cadence probably have the edge in bragging rights, having announced the tape-out of a 20nm test chip “incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node”.
In practice, this appears to mean that the two companies co-developed a flow based on Cadence Encounter and Virtuoso tools, as well some basic physical IP and a process design kit (PDK) for the 20nm process. ST used Virtuoso to generate layouts for basic IP, PLL and video DAC blocks. The 20nm PDK included features such as Modgens, constraints and space-based routing. Cadence’s Encounter tool was used to place, optimize and route the test chip, taking into account the requirements of the 20nm process.
Chi-Ping Hsu, senior vice president of research and developmen in the silicon realization group at Cadence, said: “At 20nm, custom analog IP creation and digital implementation are highly interdependent, and an optimal methodology must cover the custom analog and digital aspects of mixed-signal chip design, verification and implementation.”
Meanwhile GlobalFoundries has also been working on suppport for analog and mixed-signal design at 20nm, focusing its efforts on developing a design flow that accounts for the need to split the lithography for critical layers onto two masks (double patterning (Guide)).
While splitting regular digital features across two masks and then expecting them to align and work as advertised is a challenge, it is not at all clear what will happen to circuit performance and variability when more complex AMS features have to be split and recombined in this way.
GlobalFoundries says it has built two RTL to GDSII flows for its 20nm process, one based on Synopsys Galaxy and the other on Cadence Encounter. The flows support synthesis, ‘color aware’ place-and-route, parasitic extraction, static timing analysis, and use Mentor’s Calibre for decomposition and physical verification.
The company says that placement, routing, optimization, extraction, and physical verification all take into account the challenges and constraints that double partterning imposes. There is also an option to have the tools split the critical layers on to two masks automatically, or to handle parts of the design manually.
“Both flows are being silicon validated by designing a complex double-patterned test chip,” the company says in its press release, and are expected to be validated in silicon in early 2013, which leaves GlobalFoundries and ST in a race to move from developing design flows, doing designs and claiming tape-outs to delivering actual 20nm AMS test silicon.
GlobalFoundries will also be using DAC to show off an updated design flow for its 28nm super low power process, including AMS support. The flow uses Cadence’s Virtuoso for layout, Synopsys and Cadence for parasitic extraction, and Mentor Graphics for physical verification. The flow supports digital logic using a module from Cadence’s Encounter system.
New features include inductor synthesis and extraction support from tool vendors Lorentz Solutions, Helic and Integrand Software; variation-aware analysis using tools from Solido Design Automation; and EM/IR analysis using the Totem software platform from Apache Design.
GlobalFoundries says the flow has been validated with silicon results from an analog design running at between 300MHz and 3GHz. It also uses DRC+, which does shape-based pattern matching to identify complex manufacturing issues.