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The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.

Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.

Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.

Capital has been grown from a wire harness suite to a full electrical/electronic platform with integration for digital twin strategies.

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.