Archives

December 5, 2022

Imec pushes endurance on ferro memory at IEDM

Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations:
December 1, 2022

Identifying AI opportunities in PCB design

The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
December 1, 2022

Siemens aims to simplify compliance for Linux medical devices

New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , , , , ,   |  Organizations:
November 15, 2022

Real Intent tool looks for glitches

Real Intent has developed a tool to check design and the potential for circuits to glitch.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
November 14, 2022

Semiwise brings cryogenic models to SOI

Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
October 25, 2022

DVCon Europe keynotes focus on connectivity

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
October 17, 2022

2D advances to take center stage at IEDM

At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
October 6, 2022

Arm adds Corellium expertise for IoT to its Virtual Hardware platform

The start-ups virtualization platform has already been gaining traction in comms and security.
Article  |  Topics: Security, Tool development  |  Tags: , ,
September 27, 2022

Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , , , , ,   |  Organizations:
September 21, 2022

Nvidia proposes split-level link for chiplet interconnect

Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: