Intel talks 4 at VLSI
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
Archives
3DIC design needs more hierarchy, TSMC says
TSMC calls for modular EDA flows and increased use of hierarchical verification to support complex 3DIC designs.
TSMC certifies Aprisa for N5 and N4
TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.
Real Intent updates reset and clock-domain crossing tools
Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.
Cadence adds machine learning to electrical simulation
Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
Oxide DRAM gains traction at VLSI Symposium
VLSI Symposium 2022 will show the rapid development taking place in oxide-based replacements for traditional DRAM cells as well as the emerging area of memory-based low-power machine learning.
Imagination brings in lower-cost access for accelerator IP
Imagination Technologies has dropped the requirement to take an upfront licence for some of its IP cores if customers join its Open Access program.
Siemens brings ReadyStart RTOS to RISC-V
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Saber models aim for ADI power chips
Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
Extended coverage for sign-off analysis
Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.