Cadence gives OrCAD access to cloud AI placement
Cadence has given its new release of OrCAD access to the cloud-based AI placer designed for its Allegro PCB-layout software.
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HPC and AI provide keynote focus at DVCon Europe
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera group formed to work on federated simulation
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Verification Futures heads to the US in September
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Calibre ‘shifts left’ into place and route
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Siemens fuels custom IC flows with artificial intelligence
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
UK consortium tapes out cryo-SRAM
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
IEDM looks for leading devices for upcoming conference
The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.