X-Fab to add 130nm SiGe with IHP deal
X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.
Archives
Use equivalence checking to retarget obsolete FPGA designs
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Cybersecurity must be built in not bolted on
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Accellera attempts to standardize CDC data
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Teledyne pushes for optical for remote RF heads
Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Siemens pushes DRC to the left
Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.