Xilinx aims for software flow with Vitis

By Chris Edwards |  No Comments  |  Posted: November 12, 2019
Topics/Categories: Blog - Embedded  |  Tags: , , , ,  | Organizations:

Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.

With customers adopting AI as part of the platform, the FPGA maker sees a blurring of the skill sets. Ramine Roane, vice president of software and AI product management, said customers such as Samsung were looking to use machine learning in applications such as 5G deployment. The favoured implementation engine for AI in the forthcoming Versal family will be a programmable processor, which demands more of a software approach although the engine might talk to hardware generated using Vivado.

“Every segment we are addressing is either looking at AI or deploying AI,” Roane said.

The tools in the initial version of Vitis target the 28, 20, and 16nm generations. “We will see general availability next year for Versal,” Roane said.

To capture users in segments such as biotech, financial technology and ADAS R&D, Xilinx has take the approach that is broadly similar to that used by DSP vendors: offering libraries of parallelised functions called by a program. Runtime components, which are provided in open-source form, manage the transfer of data between the modules and I/O ports.

“Our goal is to get similar performance [to HDL]. That's why we are using libraries,” Roane said.

In Vitis, developers have access to high-level synthesis from C through the use of pragmas to define how user functions are parallelised. However, the tools are intended to be able to do loop unrolling and similar tasks automatically based on available resources.

Rob Armstrong, director of technical marketing for AI and software acceleration at Xilinx, said one issue with developing for programmable hardware remains compile time. To address this, Vitis offers an emulation environment designed to show bottlenecks and other potential problems before the engineer commits to to a hardware compile. It represents the application in terms of a data flow graph.

“We are appealing to a new market of developers who don't have a hardware background or RTL skills. We are trying to present data to them that isn't overwhelming,” Armstrong said. At the same time, he added: “The developers we are targeting are not unsophisticated. Engineers who use GPUs for acceleration understand things like cache behavior. They aren't the JavaScript guys.”

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors