DVCon US 2020 preview: Verific

By TDF Editor |  No Comments  |  Posted: February 26, 2020
Topics/Categories: Blog Topics, Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , , ,  | Organizations: ,

STOP PRESS: Please note that DVCon US has been shorted by a day because of the COVID-19 outbreak and will now end on Wednesday, March 4. An updated conference program is available here. Please use it to confirm whether events you plan to join have been moved or cancelled. Delelgates should also visit the DVCon US for details on healthcare protocols they are asked to follow.

Verific will exhibit at Booth #705 during DVCon US (DoubleTree Hotel, San Jose, Exhibition: March 2-4), offering demos that feature its SystemVerilog, VHDL and UPF Parser Platforms.

The company will also showcase ‘Verific with INVIO’. This featues the INVIO platform, with its high level, SystemVerilog- and VHDL-language agnostic Python and C++ APIs, residing on top of Verific’s standard parsers. INVIO thus streamlines a Verific user’s design environment to accelerate tool development.

A recent blog post series commemorating Verific’s 20 years included a comment from one satisfied user: “I think of Verific as a silent partner. In fact, it’s been the front end to many internal development projects that’s not obvious to the outside world. Verific’s impact on the industry has never been visible, but it’s significant.”


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