API

February 21, 2019

DVCon USA 2019 preview: Verific Design Automation

Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.

Article | Topics: Blog - EDA, - Tool development | Tags: API, C, parser, Python, SystemVerilog, UPF, VHDL | Organizations: DVCon, Verific

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