DAC 2021 preview: Verific

By TDF Editor |  No Comments  |  Posted: December 3, 2021
Topics/Categories: Conferences, Tool development, Verification  |  Tags: , , , , , , ,  | Organizations: ,

Verific, specialist in SystemVerilog, UPF and VHDL parsers and elaborators, will be present at this year’s Design Automation Conference (DAC 2021) in San Francisco during the event’s exhibition days (Exhibition: Dec 6-8; Conference Dec 5-9). It can be found at Booth #1414) in Moscone West.

Verific’s products are used by EDA, FPGA and semiconductor companies for tool development and the company will offer demos and information about its Parser Platforms.

It will highlight Verific with INVIO. The combination runs its standard parsers residing on top of the multi-API platform. INVIO provides high-level level, SystemVerilog- and VHDL-language agnostic Python and C++ APIs, and the combination is aimed at streamlining a user’s design environment to accelerate tool development.

After last year’s virtualized conference, a Verific tradition will also return. Visitors to its DAC 2021 booth will be invited to take home a stuffed giraffe in honor of the company’s mascot.

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