As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.
Keynoter Lisa Su spun a whimsical idea to serious intent as AMD looks to promote its model for heterogeneous architectures
You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.
Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.
Reviewing some of the sector's main trends with Susan Peterson, group director for VIP at the market leader.
How and why Huawei's Hisilicon and DSP specialist CEVA tapped Cadence to implement ARM protocols.
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
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